1. Field of the Invention
The present invention relates to a semiconductor package, and more particularly, to a BGA semiconductor package improving a solder joint reliability and its fabrication method.
2. Description of the Background Art
Recently, as non-memory products such as a microprocessor or a custom semiconductor (ASIC) are being rapidly requested to be more light and small, a BGA (ball grid array) semiconductor package, in which external terminals in a solder ball form advantageous for multi-pin are arranged at the bottom surface of the package, takes the lead form for semiconductor packages.
Having a concept of a PGA (pin grid array) and of a flip chip, the BGA is able to reduce the area to be occupied by the semiconductor package by approximately 60%, compared to the conventional QFP (quad flat package) semiconductor package, and its electric and heat performance is improved by 40%. Also, it is very competitive in the aspect of expense as the pins are increased in number by more than 300 pins.
The most important thing to be considered in fabricating the BGA semiconductor package is the reliability of the solder joint between the ball grid array and the printed circuit board.
Since the temperature and the thermal expansion coefficient of the ball grid array and the printed circuit board are different to each other, the element is expanded in a different ratio to the printed circuit board.
As a result, whenever the element is turned on or turned off, a high heat cyclic stress is applied to the solder joint formed between the ball grid array and the printed circuit board.
Thus, a reliability of a solder joint that overcomes such a heat cyclic stress applied to the solder joint is one of the critical factors in the development of the BGA package.
The process of fabricating of the conventional BGA adapts a technique of pad re-arrangement utilized for fabrication technique, in which the step of forming a circuit on a wafer through the step of attaching a package ball are overall processed in the fabrication process.
FIGS. 1A through 1E illustrates a sequential process of fabricating the BGA semiconductor package in accordance with the conventional art.
As shown in FIG. 1A, a chip pad 3 is formed on the upper surface of the semiconductor chip 1.
Next, as shown in FIG. 1B, a polymer insulation film 5 having a photosensitivity is coated on the upper surface of the semiconductor chip 1 by using a spin coating method, and then patterned to expose the chip pad 3.
Thereafter, as shown in FIG. 1C, for a pad re-arrangement, a metal film 7 is deposited on the upper surface of the polymer insulation film 5 and the chip pad 3, and then patterned.
And, as shown in FIG. 1D, the solder resist film 9 is coated on the upper surface of the metal film 7 and the polymer insulation film 5 by spin coating method and patterned so as to expose regions of the metal film 7 where the solder balls are to be formed.
And then, as shown in FIG. 1E, solder balls are attached in the regions exposed between the solder resist films 9 of the metal film 7, thereby completing fabrication of the BGA semiconductor package of the conventional art.
Regarding the conventional GBA semiconductor package fabricated as described above, the solder joint reliability is reduced because of the following reasons:
First, the solder ball is generally made in a manner that tin and lead have an eutectic composition. As a result, as shown in FIG. 2, the solder ball 13 is collapsed by the load of the package, causing a reduction in the length (standoff) between the pad 16 of the package and the printed circuit board 15 where the solder ball 13 is attached.
Secondly, as shown in FIG. 2, the interface area between the solder ball 13 and the pad 16 of the package or between the solder ball 13 and the printed circuit board 15 is smaller than the diameter of the solder ball 13.
Accordingly, the thermal stress caused due to the thermal expansion coefficient difference between the package and the printed circuit board is concentrated on the interfaces, resulting in occurrence of cracks 18 in the vicinity of the interface between the solder ball 13 and the pad 16 or between the solder ball 13 and the printed circuit board 15.
Thirdly, since the interface area between the solder ball 13 and the pad 16 or between the solder ball 13 and the printed circuit board 15 is small, an area allowing growth of the crack 18 generated in the vicinity of the interface is accordingly small. Thus, once the crack occurs, the reliability of the solder joint is much degraded even if the crack is not much grown.
Fourthly, in case that mounting the package on both surfaces of the printed circuit board, since the printed circuit board is warped, it is impossible to absorb the stress generated between the ball grid array and the printed circuit board, more deteriorating the reliability of the solder joint.
Therefore, an object of the present invention is to provide a BGA semiconductor package for which a flexible element is formed to absorb a heat cyclic stress applied to a solder joint formed between a ball grid array and a printed circuit substrate, thereby improving solder joint reliability, and fabrication method thereof.
To achieve these and other advantages and in accordance with the purposed of the present invention, as embodied and broadly described herein, there is provided a BGA semiconductor package including: a semiconductor chip on which a chip pad is formed; a flexible member formed on the semiconductor chip; a metal pattern formed on the upper surface of the flexible member; a connection member for electrically connecting the pad and the metal pattern; and an external terminal electrically connected to the metal pattern.
Having a metal powder, the flexible member serves as a stress buffer or a stress relief that absorbs a stress applied to a solder joint.
In order to accomplish the above object, there is also provided a method for fabricating a BGA semiconductor package including the steps of: fabricating a flexible member; forming a metal pattern on the upper surface of the flexible member; forming a pad on the upper surface of the semiconductor chip; attaching the flexible member onto the semiconductor chip in a manner that the pad is exposed; electrically connecting the pad and the metal pattern; and attaching an external terminal onto a predetermined region of the metal pattern.